-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM		"Quartus II 64-Bit"
-- VERSION		"Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
-- CREATED		"Sun Jun 16 19:12:23 2024"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY cpu IS 
	PORT
	(
		reset :  IN  STD_LOGIC;
		clock :  IN  STD_LOGIC;
		ALUOUT1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
		ALUOUT2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
		ALUOUT3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
		ALUOUT4 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
		ALUOUT5 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
		ALUOUT6 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
		s :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END cpu;

ARCHITECTURE bdf_type OF cpu IS 

COMPONENT pc
	PORT(clk : IN STD_LOGIC;
		 Reset : IN STD_LOGIC;
		 LOAD_PC : IN STD_LOGIC;
		 INCR_PC : IN STD_LOGIC;
		 Addr_Val_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 PC_out : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END COMPONENT;

COMPONENT seg7_16b
	PORT(Blank : IN STD_LOGIC;
		 Test : IN STD_LOGIC;
		 Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 RQ1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
		 RQ2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END COMPONENT;

COMPONENT im_double
	PORT(exop : IN STD_LOGIC;
		 in_c : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 out_c : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END COMPONENT;

COMPONENT mux2to1_16
	PORT(sel : IN STD_LOGIC;
		 d0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 d1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END COMPONENT;

COMPONENT rom
	PORT(clock : IN STD_LOGIC;
		 address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END COMPONENT;

COMPONENT op_de
	PORT(OP : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 WE : OUT STD_LOGIC;
		 Smux : OUT STD_LOGIC;
		 Exop : OUT STD_LOGIC;
		 str : OUT STD_LOGIC;
		 ld : OUT STD_LOGIC;
		 Lmux : OUT STD_LOGIC;
		 PC_1 : OUT STD_LOGIC;
		 wpc : OUT STD_LOGIC;
		 beq : OUT STD_LOGIC;
		 bne : OUT STD_LOGIC;
		 bgt : OUT STD_LOGIC;
		 jump : OUT STD_LOGIC;
		 R_type : OUT STD_LOGIC;
		 W_rom : OUT STD_LOGIC;
		 Imux : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
		 S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;

COMPONENT reg_rw_mux2to1
	PORT(sel : IN STD_LOGIC;
		 d0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		 d1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		 y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
	);
END COMPONENT;

COMPONENT alu_8b
	PORT(A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 S : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		 CO : OUT STD_LOGIC;
		 ZF : OUT STD_LOGIC;
		 F : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END COMPONENT;

COMPONENT sec_decoder
	PORT(OP : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		 S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;

COMPONENT mux2to1
	PORT(sel : IN STD_LOGIC;
		 d0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		 d1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		 y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;

COMPONENT registers
	PORT(WE : IN STD_LOGIC;
		 Clk : IN STD_LOGIC;
		 bus_W : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 RA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		 RB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		 RW : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		 busA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
		 busB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END COMPONENT;

COMPONENT ram
	PORT(wren : IN STD_LOGIC;
		 rden : IN STD_LOGIC;
		 clock : IN STD_LOGIC;
		 address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END COMPONENT;

SIGNAL	beq :  STD_LOGIC;
SIGNAL	bgt :  STD_LOGIC;
SIGNAL	bne :  STD_LOGIC;
SIGNAL	Data_A :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	Data_B :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	Exop :  STD_LOGIC;
SIGNAL	F :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	IY_OUT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	JUMP :  STD_LOGIC;
SIGNAL	Lmux :  STD_LOGIC;
SIGNAL	PC_1 :  STD_LOGIC;
SIGNAL	PC_out :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	q :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	R_type :  STD_LOGIC;
SIGNAL	S_ALTERA_SYNTHESIZED :  STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL	Smux :  STD_LOGIC;
SIGNAL	str :  STD_LOGIC;
SIGNAL	W_rom :  STD_LOGIC;
SIGNAL	WE :  STD_LOGIC;
SIGNAL	wpc :  STD_LOGIC;
SIGNAL	write_R :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_15 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_16 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_17 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;


BEGIN 
SYNTHESIZED_WIRE_16 <= '0';
SYNTHESIZED_WIRE_17 <= '1';



b2v_inst : pc
PORT MAP(clk => SYNTHESIZED_WIRE_15,
		 Reset => reset,
		 LOAD_PC => JUMP,
		 INCR_PC => PC_1,
		 Addr_Val_in => F,
		 PC_out => PC_out);


b2v_inst10 : seg7_16b
PORT MAP(Blank => SYNTHESIZED_WIRE_16,
		 Test => SYNTHESIZED_WIRE_17,
		 Data => F(15 DOWNTO 8),
		 RQ1 => ALUOUT3,
		 RQ2 => ALUOUT4);




b2v_inst15 : im_double
PORT MAP(exop => Exop,
		 in_c => IY_OUT(7 DOWNTO 0),
		 out_c => SYNTHESIZED_WIRE_3);


b2v_inst16 : mux2to1_16
PORT MAP(sel => R_type,
		 d0 => SYNTHESIZED_WIRE_3,
		 d1 => Data_B,
		 y => SYNTHESIZED_WIRE_5);


b2v_inst17 : rom
PORT MAP(clock => SYNTHESIZED_WIRE_4,
		 address => PC_out,
		 q => IY_OUT);


b2v_inst18 : op_de
PORT MAP(OP => IY_OUT,
		 WE => WE,
		 Smux => Smux,
		 Exop => Exop,
		 Lmux => Lmux,
		 PC_1 => PC_1,
		 jump => JUMP,
		 R_type => R_type,
		 W_rom => W_rom,
		 S => SYNTHESIZED_WIRE_6);


SYNTHESIZED_WIRE_15 <= Smux OR clock;


b2v_inst20 : reg_rw_mux2to1
PORT MAP(sel => R_type,
		 d0 => IY_OUT(9 DOWNTO 8),
		 d1 => IY_OUT(7 DOWNTO 6),
		 y => SYNTHESIZED_WIRE_9);


b2v_inst21 : alu_8b
PORT MAP(A => Data_A,
		 B => SYNTHESIZED_WIRE_5,
		 S => S_ALTERA_SYNTHESIZED,
		 F => F);


b2v_inst22 : sec_decoder
PORT MAP(OP => IY_OUT(2 DOWNTO 0),
		 S => SYNTHESIZED_WIRE_7);


b2v_inst24 : mux2to1
PORT MAP(sel => R_type,
		 d0 => SYNTHESIZED_WIRE_6,
		 d1 => SYNTHESIZED_WIRE_7,
		 y => S_ALTERA_SYNTHESIZED);


SYNTHESIZED_WIRE_4 <= NOT(SYNTHESIZED_WIRE_15);



b2v_inst256 : registers
PORT MAP(WE => WE,
		 Clk => clock,
		 bus_W => write_R,
		 RA => IY_OUT(11 DOWNTO 10),
		 RB => IY_OUT(9 DOWNTO 8),
		 RW => SYNTHESIZED_WIRE_9,
		 busA => Data_A,
		 busB => Data_B);


b2v_inst258 : seg7_16b
PORT MAP(Blank => SYNTHESIZED_WIRE_16,
		 Test => SYNTHESIZED_WIRE_17,
		 Data => PC_out(7 DOWNTO 0),
		 RQ1 => ALUOUT5,
		 RQ2 => ALUOUT6);


b2v_inst27 : mux2to1_16
PORT MAP(sel => Lmux,
		 d0 => F,
		 d1 => q,
		 y => write_R);


b2v_inst29 : ram
PORT MAP(wren => SYNTHESIZED_WIRE_12,
		 rden => WE,
		 clock => clock,
		 address => F,
		 data => Data_B,
		 q => q);


SYNTHESIZED_WIRE_12 <= NOT(WE);



b2v_inst32 : mux2to1_16
PORT MAP(sel => W_rom,
		 d0 => Data_A,
		 d1 => Data_B);



b2v_inst9 : seg7_16b
PORT MAP(Blank => SYNTHESIZED_WIRE_16,
		 Test => SYNTHESIZED_WIRE_17,
		 Data => F(7 DOWNTO 0),
		 RQ1 => ALUOUT1,
		 RQ2 => ALUOUT2);

s <= S_ALTERA_SYNTHESIZED;

END bdf_type;